1. Field of the Invention
Embodiments of the invention generally provide a substrate support utilized in semiconductor processing and a method of fabricating the same.
2. Description of the Background Art
Liquid crystal displays or flat panels are commonly used for active matrix displays such as computer and television monitors, personal digital assistants (PDAs), cell phones and the like. Generally, flat panels comprise two glass plates having a layer of liquid crystal material sandwiched therebetween. At least one of the glass plates includes at least one conductive film disposed thereon that is coupled to a power supply. Power supplied to the conductive film from the power supply changes the orientation of the crystal material, creating a pattern such as text or graphics seen on the display. One fabrication process frequently used to produce flat panels is plasma enhanced chemical vapor deposition (PECVD).
Plasma enhanced chemical vapor deposition is generally employed to deposit thin films on a substrate such as a flat panel or semiconductor wafer. Plasma enhanced chemical vapor deposition is generally accomplished by introducing a precursor gas into a vacuum chamber that contains a substrate. The precursor gas is typically directed through a distribution plate situated near the top of the chamber. The precursor gas in the chamber is energized (e.g., excited) into a plasma by applying RF power to the chamber from one or more RF sources coupled to the chamber. The excited gas reacts to form a layer of material on a surface of the substrate that is positioned on a temperature controlled substrate support. In applications where the substrate receives a layer of low temperature polysilicon, the substrate support may be heated in excess of 400 degrees Celsius. Volatile by-products produced during the reaction are pumped from the chamber through an exhaust system.
Generally, large area substrates utilized for flat panel fabrication are large, often exceeding 550 mm×650 mm, and are envisioned up to and beyond 4 square meters in surface area. Correspondingly, the substrate supports utilized to process large area substrates are proportionately large to accommodate the large surface area of the substrate. The substrate supports for high temperature use typically are casted, encapsulating one or more heating elements and thermocouples in an aluminum body. Due to the size of the substrate support, one or more reinforcing members are generally disposed within the substrate support to improve the substrate support's stiffness and performance at elevated operating temperatures (i.e., in excess of 350 degrees Celsius and approaching 500 degrees Celsius to minimize hydrogen content in some films). The aluminum substrate support is then anodized to provide a protective coating.
Although substrate supports configured in this manner have demonstrated good processing performance, small local variations in film thickness, often manifesting as spots of thinner film thickness, have been observed which may be detrimental to the next generation of devices formed on large area substrates. It is believed that variation is glass thickness and flatness, along with a smooth substrate support surface, typically about 50 micro-inches, creates a local capacitance variation in certain locations across the glass substrate, thereby creating local plasma non-uniformities that result on deposition variation, e.g., spots of thin deposited film thickness. Aging and modifying plasma conditioning of the substrate support has shown to mitigate thin spot formation, particularly when performed in conjunction with an extended chamber vacuum purge before transferring a substrate into the chamber for processing. However, the resultant expenditures of time and materials required by this method and its unfavorable effect on cost and throughput make obtaining a more effective solution desirable.
As substrates sizes have increased from sizes from about 370 mm×470 mm to about 1200 mm×1040 mm, or even 1800 mm×2200 mm, other new defect modes have become critical issues in the fabrication of the flat panel display devices. As the size of next generation of substrates continue to grow, the importance of defect reduction becomes increasingly important due to the substantial investment by the flat panel manufacturer in each substrate. Moreover, with the continual evolution of device critical dimension reduction demanding closer tolerances for film uniformity, the reduction and/or elimination of film thickness variation becomes an important factor for the economic production of the next generation devices formed on large area substrates.
Moreover, the effectiveness of a substrate fabrication process is often measured by two related and important factors, which are device yield and the cost of ownership (CoO). These factors are important since they directly affect the cost to produce an electronic device and thus a device manufacturer's competitiveness in the market place. The CoO, while affected by a number of factors, is greatly affected by the initial cost of the processing hardware and the replacement cost of consumable hardware. In an effort to reduce CoO, electronic device manufacturers often spend a large amount of time trying to optimize the processing hardware and consumable cost to achieve the greatest the highest profit margins without affecting the particle and process yield performance. Another important factor in the CoO calculation is the system reliability and system uptime. These factors are very important to a cluster tool's profitability and/or usefulness, since the longer the system is unable to process substrates the more money is lost by the user due to the lost opportunity to process substrates in the cluster tool. Therefore, cluster tool users and manufacturers spend a large amount of time trying to develop reliable processes, reliable hardware and reliable systems that have increased uptime.
One defect that has been found to be an issue in large area substrate PECVD type processes is a defect known in the industry as the electro-static discharge (ESD) metal line arcing problem. It is believed that as the substrate size increased the inductive current induced in the longer and larger ESD metal lines during plasma deposition is large enough to make the damage to the substrate from plasma induced arching a major recurring problem. This problem is generally not experienced in the smaller semiconductor device fabrication applications (e.g., 150 mm to 300 mm circular silicon substrates) since the gate-metal lines in flat panel display applications, which are connected to the ESD discharge line, are generally about 5 to 10 micrometers (μm) wide and can be about a meter or two meters long whereas in typical semiconductor application gate-metal lines are on the order of 90 nanometers size at most tens of millimeters long. The width of the ESD lines in the flat panel display substrates is typically greater than 1 mm in size and can be between about a meter or two meters long. It is believed that the ESD metal lines in flat panel display applications thus tend to act as an antenna that can collect an amount of charge during plasma processing that will cause arching damage to the substrate. Therefore, there is a greater need to reduce the chance of arcing due to the interaction with the plasma by increasing the resistance of the discharge path to ground. It should be noted that the thickness of the flat panel substrates (e.g., 0.7 mm), which is much larger than semiconductor substrates, has not changed dramatically from the large and smaller sized flat panel display type substrates.
Another defect that has arisen in the processing of 1200 mm×1040 mm, or larger substrates, is an increased in the number of particles found on the backside of the substrate after performing a plasma process on the substrate, such as a PECVD process. It is believed that as the glass substrate size increases the ability to trap static charge during plasma processing increases, thus causing particles found in the processing chamber to be attracted to the substrate surface where they are held by the trapped charge.
The issue of arcing and static charge is believed to be different in flat panel display applications versus semiconductor applications due to the size and properties of the different substrate materials. The static charge generated by the triboelectric process, or the process of bringing two materials into contact with each other and then separating them from each other, is influenced by a number of factors, two of which are the amount of surface contact between the two components and the work function of the two materials. One difference between flat panel and semiconductor applications is the difference in the properties of the substrate material(s) used in each of these applications (e.g., glass versus silicon (or germanium)), which is related to a material property known as its work function. In general, the work function describes a material's ability to hold onto its free electrons (the electrons orbiting the outer most shell of the material). In general, materials with larger work functions (e.g., silicon) are less likely to give up their electrons than a material that has a lower work function (e.g. glass) when they are placed in contact with a given material and then separated from the material. (See reference “Triboelectric Generation: Getting Charged” in EE-Evaluation Engineering, November, 2000 written by Ryne C. Allen.) Therefore, while the static charge generation issue is dependent on the materials which the processed substrate comes in contact with, the amount of charge and the polarity of the charge generated in a flat panel display substrate versus a semiconductor substrate will not be the same.
The second triboelectric factor, or the amount of contact between the parts, means that the greater the contact between the components the more charge that will be transferred between the contacting components and possibly arcing. The amount of surface roughness of the two components has a direct affect on the amount of contact between the two parts. Therefore, while some prior art application, such as U.S. Pat. No. 6,063,203 filed Jun. 2, 1998 suggest a process of roughening the surface of a susceptor (substrate support) to an Ra of between 1 and 8 micrometers, the reference requires a final step of polishing the roughened susceptor surface which reduces the roughness and increase the contact between the two substrate components. The reduced roughness, and thus increased contact between the two substrate components, will increase the triboelectric charge transfer between the substrate and the substrate support, thus increasing the likelihood of generating enough trapped charge to form an arc or attract particles. An alternate theory is that the step of polishing a roughened surface, as described in the prior art, is thought to remove some of the benefits received from roughening the surface of the substrate support, such as an improved electrical contact between the two parts (i.e., susceptor surface and glass substrate). The improved electrical contact is believed to be created by the higher contact stress at the sharp tips or high points of the roughened surface, which is thought to reduce the charge buildup between the two parts during plasma processing, thus reducing the chance of arcing and particle attraction to the substrate surfaces.
Therefore, there is a need for an improved substrate support that resolves all of these issues raised above.